Abstract [eng] |
A first chapter deals with FPGA (field programmable gate arrays) structure. There are examined FPGA gates, input and output devices, an routing inside devices. Further an analysis of Altera's NIOS II soft processor, which is obtained by uploading the NIOS II code into the FPGA, is done. Altera's NIOS II is a general-purpose programmable, 32-bit RISC processor optimized for programmable logic. |